The present invention relates generally to testing integrated circuits, and more specifically, to an iterative N-detect based logic diagnostic method.
A fault model is an engineering model of defects that occur in the fabrication of an integrated circuit, such as a microprocessor having numerous interconnected logic circuits. It is appreciated that many types of defects may be modeled in the fault model. Basic fault models in digital circuits may include the following. 1) The stuck-at fault model. A signal, or gate output, is stuck at a 0 or 1 value, independent of the inputs to the circuit. 2) The bridging fault model. Two signals are connected together when they should not be. Depending on the logic circuitry employed, this may result in a wired-OR or wired-AND logic function. 3) Transistor faults. This model is used to describe faults for complementary metal-oxide-semiconductor (CMOS) logic gates. At transistor level, a transistor maybe stuck-short or stuck-open. In stuck-short, a transistor behaves as it is always conducts (or stuck-on), and stuck-open is when a transistor never conducts current (or stuck-off). Stuck-short will produce a short between VDD (positive supply voltage) and VSS (negative supply voltage or ground). 4) The open fault model. Here a wire is assumed broken, and one or more inputs are disconnected from the output that should drive them. As with bridging faults, the resulting behavior depends on the circuit implementation. 5) The delay fault model, where the signal eventually assumes the correct value, but more slowly (or rarely, more quickly) than normal.